India is setting its sights on advanced semiconductor manufacturing with plans to produce 3-nanometre and eventually 2-nanometre chips by the early 2030s. Union IT Minister Ashwini Vaishnaw outlined the vision while interacting with startups supported under the Design Linked Incentive (DLI) scheme on January 27, calling it the next phase of the country’s semiconductor roadmap.
Speaking about India’s near-term progress, Vaishnaw said the country would achieve strong chip design and manufacturing capabilities by the end of this decade. “As we go into 2029, we will have a major capability of manufacturing and designing the chips which are required practically in 70–75 per cent of all applications in our country. The next level should come by 2032… to reach 3nm chips manufacturing,” he said.
Vaishnaw noted that the journey towards 3nm and 2nm manufacturing would form a core pillar of the upcoming Semicon 2.0 programme. The roadmap, he explained, is being shaped by studying how countries such as South Korea, Taiwan and Japan successfully built their semiconductor ecosystems over time.
Addressing startups at the DLI 1.0 showcase, the minister said the government’s initial strategy of providing access to EDA tools, IP libraries and multi-project wafer (MPW) support had delivered tangible results. “So many of you (startups) have taped out and validated your products. Many of you have found markets,” he said.
India currently has 24 startups supported under the DLI scheme, and the next phase aims to scale this number to at least 50 fabless semiconductor companies.
(Photo by Vishnu Mohanan on Unsplash)
Under DLI 2.0, which will be integrated into Semicon 2.0, government support will be concentrated around six key chip categories – compute, RF, networking, power management, sensors and memory.
Highlighting the strategic importance of these segments, Vaishnaw said, “With these six, we can build any major system — whether it is defence, missiles, railways or automobiles.”
He also shared details on manufacturing infrastructure. Tape-out facilities for mature nodes such as 180nm will be anchored at SCL Mohali, while advanced nodes down to 28nm will be supported through the upcoming Tata semiconductor fab in Dholera.
Vaishnaw said feedback from startups participating in DLI 1.0 would play a direct role in shaping the next iteration of the scheme, including decisions on which areas should receive continued or expanded support.
During the event, founders highlighted several challenges, including the need for stronger backing for analog and RF intellectual property, preferential market access in strategic sectors, and financial support to bridge costs until production volumes scale up.
Startups showcased chips already in tape-out or testing stages across AI, RF and broadband applications. Trivandrum-based Netra Semiconductor said its A2000 AI application processor taped out on TSMC’s 12nm node in October and is currently undergoing silicon testing, while its R1000 AI-MCU is expected to tape out next month.
RF IC startup Fermionix pointed to demand from defence and satellite communication customers for its X-band radar chips and sought government assistance to expand into Ku- and Ka-band offerings. InCore Semiconductor, founded by members of the IIT-Madras SHAKTI processor team, reiterated its focus on RISC-V-based solutions and called for preferential market access in critical sectors.
Vaishnaw also announced that the government will introduce Deep Tech Awards in 2026, covering sectors such as semiconductors, AI, space and biotechnology.
Summing up the long-term ambition, he said, “With Semicon 2.0, we will have a major part of the programme dedicated to reaching the 3nm and 2nm goal. By 2035, we should be among the top four semiconductor nations in the world.”
Answer. India aims to produce 3nm chips by 2032 and eventually 2nm chips by the early 2030s.
Answer. Semicon 2.0 will anchor India’s advanced chip ambitions, supporting six key categories: compute, RF, networking, power management, sensors, and memory.
Answer. Startups receive access to EDA tools, IP libraries, MPW support, and will be scaled to at least 50 fabless semiconductor companies under DLI 2.0.
https://www.mymobileindia.com/trai-needs-more-teeth-to-punish-and-enforce-ashwini-vaishnaw/
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